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Final Electrical Specifications
LTC1418 Low Power, 14-Bit, 200ksps ADC with Serial and Parallel I/O
January 1998
FEATURES
s s s s s s s s s s s s
DESCRIPTION
The LTC (R)1418 is a low power, 200ksps, 14-bit A/D converter. Data output is selectable for 14-bit parallel or serial format. This versatile device can operate from a single 5V or 5V supply. An onboard high performance sample-and-hold, a precision reference and internal timing minimize external circuitry requirements. The low 15mW power dissipation is made even more attractive with two user selectable power shutdown modes. The LTC1418 converts 0V to 4.096V unipolar inputs from a single 5V supply and 2.048V bipolar inputs from 5V supplies. DC specs include 1.5LSB INL, 1LSB DNL and no missing codes over temperature. Outstanding AC performance includes 82dB S/(N + D) and 95dB THD at the Nyquist input frequency of 100kHz. The flexible output format allows either parallel or serial I/O. The SPI/MICROWIRETM compatible serial I/O port can operate as either master or slave and can support clock frequencies from DC to 10MHz. A separate convert start input and a data ready signal (BUSY) allow easy control of conversion start and data transfer.
, LTC and LT are registered trademarks of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation.
Single Supply 5V or 5V Operation Sample Rate: 200ksps 1.5LSB INL and 1LSB DNL Max Power Dissipation: 15mW (Typ) Parallel or Serial Data Output No Missing Codes Over Temperature Power Shutdown: Nap and Sleep External or Internal Reference Differential High Impedance Analog Input Input Range: 0V to 4.096V or 2.048V 82dB S/(N + D) and 95dB THD at Nyquist 28-Pin SSOP Package
APPLICATIONS
s s s s s s
Remote Data Acquisition Battery Operated Systems Digital Signal Processing Isolated Data Acquisition Systems Audio and Telecom Processing Medical Instrumentation
TYPICAL APPLICATION
Low Power, 200kHz, 14-Bit Sampling A/D Converter
5V 10F VDD LTC1418 AIN+ S/H AIN - 14-BIT ADC 14 SELECTABLE SERIAL/ PARALLEL PORT D5 D4 (EXTCLKIN) D3 (SCLK) D2 (CLKOUT) D1 (DOUT) D0 (EXT/INT) SER/PAR D13
1.0
0.5 INL (LSBs)
4.096V REFCOMP 10F BUFFER
-0.5
8k VREF 1F AGND VSS (0V OR - 5V) DGND
1418 TA01
2.5V REFERENCE
TIMING AND LOGIC
BUSY CS RD CONVST SHDN
-1.0 0 4896 8192 OUTPUT CODE
1418 TA02
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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0
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Typical INL Curve
12288
16384
1
LTC1418
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
PACKAGE/ORDER INFORMATION
TOP VIEW AIN+ AIN - VREF REFCOMP AGND D13 (MSB) D12 D11 D10 1 2 3 4 5 6 7 8 9 28 VDD 27 VSS 26 BUSY 25 CS 24 CONVST 23 RD 22 SHDN 21 SEP/PAR 20 D0 (EXT/INT) 19 D1 (DOUT) 18 D2 (CLKOUT) 17 D3 (SCLK) 16 D4 (EXTCLKIN) 15 D5
Supply Voltage (VDD) ................................................. 6V Negative Supply Voltage (VSS) Bipolar Operation Only ........................... - 6V to GND Total Supply Voltage (VDD to VSS) Bipolar Operation Only ....................................... 12V Analog Input Voltage (Note 3) Unipolar Operation .................. - 0.3V to (VDD + 0.3V) Bipolar Operation........... (VSS - 0.3V) to (VDD + 0.3V) Digital Input Voltage (Note 4) Unipolar Operation ................................- 0.3V to 10V Bipolar Operation.........................(VSS - 0.3V) to 10V Digital Output Voltage Unipolar Operation .................. - 0.3V to (VDD + 0.3V) Bipolar Operation........... (VSS - 0.3V) to (VDD + 0.3V) Power Dissipation.............................................. 500mW Operation Temperature Range ..................... 0C to 70C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC1418ACG LTC1418CG
D9 10 D8 11 D7 12 D6 13 DGND 14
G PACKAGE 28-LEAD PLASTIC SSOP
TJMAX = 110C, JA = 95C/ W (G) TJMAX = 110C, JA = 100C/ W (N)
Consult factory for Industrial grade, Military grade and N package parts.
CO VERTER CHARACTERISTICS
PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Full-Scale Error Full-Scale Tempco (Note 8) Internal Reference External Reference = 2.5V IOUT(REF) = 0, Internal Reference IOUT(REF) = 0, External Reference (Note 7) CONDITIONS
With internal reference (Notes 5, 6)
MIN
q q q q
LTC1418 TYP MAX 0.8 0.7 5 10 5 2 1.5 20 60 30
MIN 14
LTC1418A TYP MAX 0.5 0.35 2 20 5 10 1 1.25 1 10 60 15 45
UNITS Bits LSB LSB LSB LSB LSB ppm/C ppm/C
13
q
15 5
A ALOG I PUT
SYMBOL PARAMETER VIN IIN CIN tACQ
(Note 5)
CONDITIONS 4.75V VDD 5.25V (Unipolar) 4.75V VDD 5.25V, - 5.25V VSS - 4.75V (Bipolar) CS = High Between Conversions (Sample Mode) During Conversions (Hold Mode) Commercial Industrial
q q q q q
MIN
TYP 0 to 4.096 2.048
MAX
UNITS V V
Analog Input Range (Note 9) Analog Input Leakage Current Analog Input Capacitance Sample-and-Hold Acquisition Time
1 25 5 300 300 1000 1000
2
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WW
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A pF pF ns ns
LTC1418
DY A IC ACCURACY
SYMBOL PARAMETER S/(N + D) Signal-to-Noise Plus Distortion Ratio THD SFDR IMD Total Harmonic Distortion Spurious Free Dynamic Range Intermodulation Distortion Full Power Bandwidth Full Linear Bandwidth
I TER AL REFERE CE CHARACTERISTICS
PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Output Resistance CONDITIONS IOUT = 0 IOUT = 0 4.75V VDD 5.25V - 5.25V VSS - 4.75V 0.1mA IOUT 0.1mA
DIGITAL I PUTS AND OUTPUTS
SYMBOL PARAMETER VIH VIL IIN CIN VOH VOL IOZ COZ ISOURCE ISINK High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage D13 to D0 Hi-Z Output Capacitance D13 to D0 Output Source Current Output Sink Current
POWER REQUIRE E TS
SYMBOL PARAMETER VDD VSS IDD Positive Supply Voltage (Notes 10, 11) Negative Supply Voltage (Note 10) Positive Supply Current
ISS
Negative Supply Current Nap Mode Sleep Mode
PDIS
Power Dissipation
UW
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(Note 5)
CONDITIONS 100kHz Input Signal 100kHz Input Signal, First 5 Harmonics 100kHz Input Signal fIN1 = 97.7kHz, fIN2 = 104.2kHz S/(N + D) 77dB
q q q
MIN 79 86
TYP 82 - 95 95 - 90 5 0.5
MAX - 86
UNITS dB dB dB dB MHz MHz
U
(Note 5)
MIN 2.480
q
TYP 2.500 10 0.05 0.05 8
MAX 2.520 45
UNITS V ppm/C LSB/ V LSB/ V k
(Note 5)
MIN
q q q
CONDITIONS VDD = 5.25V VDD = 4.75V VIN = 0V to VDD VDD = 4.75V, IO = - 10A VDD = 4.75V, IO = - 200A VDD = 4.75V, IO = 160A VDD = 4.75V, IO = 1.6mA VOUT = 0V to VDD, CS High CS High (Note 9) VOUT = 0V VOUT = VDD
TYP
MAX 0.8 10
UNITS V V A pF V V
2.4
5 4.74
q q q q
4.0 0.05 0.10 0.4 10 15 - 10 10
V V A pF mA mA
(Note 5)
CONDITIONS Bipolar Only (VSS = 0V for Unipolar) Unipolar, RD High (Note 5) Bipolar, RD High (Note 5) SHDN = 0V, CS = 0V (Note 12) SHDN = 0V, CS = 5V (Note 12) Bipolar, RD High (Note 5) SHDN = 0V, CS = 0V (Note 12) SHDN = 0V, CS = 5V (Note 12) Unipolar Bipolar
q q
MIN 4.75 - 4.75
TYP
MAX 5.25 - 5.25
UNITS V V mA mA A A mA A A mW mW
Nap Mode Sleep Mode
3 3.4 570 2 1.4 0.1 0.1 15 24
4 4
q
1.8
q q
20 29
3
LTC1418
TI I G CHARACTERISTICS
SYMBOL fSAMPLE(MAX) tCONV tACQ tACQ + tCONV t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 PARAMETER Maximum Sampling Frequency Conversion Time Acquisition Time Acquisition Plus Conversion Time CS to RD Setup Time CS to CONVST Setup Time CS to SHDN Setup Time to Ensure Nap Mode SHDN to CONVST Wake-Up Time from Nap Mode CONVST Low Time CONVST to BUSY Delay Data Ready Before BUSY
q
t11
t12 t13 t14 t15
The q denotes specifications which apply over the full operating temperature range; all other limits and typicals TA = 25C. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND and AGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below VSS or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS or above VCC without latchup. Note 4: When these pin voltages are taken below VSS they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS without latchup. These pins are not clamped to VDD. Note 5: VDD = 5V, VSS = 0V or - 5V, fSAMPLE = 200kHz, tr = tf = 5ns unless otherwise specified. Note 6: Linearity, offset and full-scale specifications apply for a singleended input with AIN- grounded.
4
UW
(Note 5)
CONDITIONS
q q q q
MIN 200
TYP 3.4 0.3 3.7
MAX 4 1 5
UNITS kHz s s s ns ns ns
(Notes 9, 10) (Notes 9, 10) (Notes 9, 10) (Note 10) (Notes 10, 11) CL = 25pF
q q q
0 40 40 500 40 35 20 15 500 -5 15 30 40 40 55 20 25 30 35 70
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
q q
Delay Between Conversions Wait Time RD After BUSY Data Access Time After RD
(Note 10) CL = 25pF
q q q
CL = 100pF
q
20 8
Bus Relinquish Time Commercial Industrial RD Low Time CONVST High Time Delay Time, SCLK to DOUT Valid Time from Previous Data Remain Valid After SCLK CL = 25pF (Note 9) CL = 25pF (Note 9)
q q q q q
t10 40 35 15 25 70
ns ns
Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Bipolar offset is the offset voltage measured from - 0.5LSB when the output code flickers between 0000 0000 0000 00 and 1111 1111 1111 11. Note 9: Guaranteed by design, not subject to test. Note 10: Recommended operating conditions. Note 11: The falling edge of CONVST starts a conversion. If CONVST returns high at a critical point during the conversion, it can create small errors. For best performance ensure that CONVST returns high either within 2.1s after the conversion starts or after BUSY rises. Note 12: Pins 16 (D4/EXTCLKIN), 17 (D3/SCLK) and 20 (DO/EXT/INT) at 0V or 5V. See Power Shutdown.
LTC1418
PIN FUNCTIONS
AIN+ (Pin 1): Positive Analog Input. AIN- (Pin 2): Negative Analog Input. VREF (Pin 3): 2.50V Reference Output. Bypass to AGND with 1F. REFCOMP (Pin 4): 4.096V Reference Bypass Pin. Bypass to AGND with 10F tantalum in parallel with 0.1F ceramic. AGND (Pin 5): Analog Ground. D13 to D6 (Pins 6 to 13): Three-State Data Outputs (Parallel). D13 is the most significant bit. DGND (Pin 14): Digital Ground for Internal Logic. Tie to AGND. D5 (Pin 15): Three-State Data Output (Parallel). D4 (EXTCLKIN) (Pin 16): Three-State Data Output (Parallel). Conversion clock input (serial) when Pin 20 (EXT/INT) is tied to high. D3 (SCLK) (Pin 17): Three-State Data Output (Parallel). Data clock input (serial). D2 (CLKOUT) (Pin 18): Three-State Data Output (Parallel). Conversion clock output (serial). D1 (DOUT) (Pin 19): Three-State Data Output (Parallel). Serial data output (serial). D0 (EXT/INT) (Pin 20): Three-State Data Output (Parallel). Conversion clock selector (serial). An input low enables the internal conversion clock. An input High indicates an external conversion clock will be assigned to Pin 16 (EXTCLKIN). SER/PAR (Pin 21): Date Output Mode. SHDN (Pin 22): Power Shutdown Input. Low selects shutdown. Shutdown mode selected by CS. CS = 0 for nap mode and CS = 1 for sleep mode. RD (Pin 23): Read Input. This enables the output drivers when CS is low. CONVST (Pin 24): Conversion Start Signal. This active low signal starts a conversion on its falling edge. CS (Pin 25): Chip Select. This input must be low for the ADC to recognize the CONVST and RD inputs. CS also sets the shutdown mode when SHDN goes low. CS and SHDN low select the quick wake-up nap mode. CS high and SHDN low select sleep mode. BUSY (Pin 26): The BUSY Output Shows the Converter Status. It is low when a conversion is in progress. VSS (Pin 27): Negative Supply, - 5V for Bipolar Operation. Bypass to AGND with 10F tantalum in parallel with 0.1F ceramic. Analog ground for unipolar operation. VDD (Pin 28): 5V Positive Supply. Bypass to AGND with 10F tantalum in parallel with 0.1F ceramic.
FUNCTIONAL BLOCK DIAGRA
AIN+
AIN- VREF 2.5V 8k 2.5V REF ZEROING SWITCHES
REF AMP
REFCOMP AGND DGND
4.096V SUCCESSIVE APPROXIMATION REGISTER INTERNAL CLOCK 14 SHIFT REGISTER * * * D13 D0 D3/(SCLK) MUX CONTROL LOGIC D1/(DOUT)
1418 BD
D4 (EXTCLKIN)
D0 (EXT/INT) SHDN CONVST RD CS SER/PAR D2/(CLKOUT) BUSY
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CSAMPLE
CSAMPLE
VDD: 5V VSS: 0V FOR UNIPOLAR MODE - 5V FOR BIPOLAR MODE
+
14-BIT CAPACITIVE DAC COMP
NOTE: PIN NAMES IN PARENTHESES REFER TO SERIAL MODE
-
5
LTC1418
TEST CIRCUITS
Load Circuits for Access Timing
5V 1k DBN 1k DGND A) HI-Z TO VOH AND VOL TO VOH CL DBN CL DGND B) HI-Z TO VOL AND VOH TO VOL
1418 TC01
Load Circuits for Output Float Delay
5V 1k DBN 1k 30pF DBN 30pF
A) VOH TO HI-Z
B) VOL TO HI-Z
1418 TC02
APPLICATIONS INFORMATION
Driving the Analog Input The differential analog inputs of the LTC1418 are easy to drive. The inputs may be driven differentially or as a singleended input (i.e., the AIN- input is grounded). The AIN+ and AIN- inputs are sampled at the same instant. Any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sampleand-hold circuit. The inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. During conversion, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low then the LTC1418 inputs can be driven directly. As source impedance increases so will acquisition time (see Figure 1). For minimum acquisition time, with high source impedance, a buffer amplifier must be used. The only requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts -- 1s for full throughput rate. Choosing an Input Amplifier Choosing an input amplifier is easy if a few requirements are taken into consideration. First, choose an amplifier that has a low output impedance (<100) at the closed-loop bandwidth frequency. For example, if an amplifier is used in a gain of 1 and has a closed-loop bandwidth of 10MHz, then the output impedance at 10MHz must be less than 100. The second requirement is that the closed-loop
ACQUISITION TIME (s)
6
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100
10
1
0.1 0.001
0.01 0.1 1 10 SOURCE RESISTANCE (k)
100
1418 F01
Figure 1. tACQ vs Source Resistance
bandwidth must be greater than 5MHz to ensure adequate small-signal settling for full throughput rate. If slower op amps are used, more settling time can be provided by increasing the time between conversions. Suitable devices capable of driving the ADC's input include the LT(R)1354 and LT1357 op amps. The noise and the distortion of the input amplifier must also be considered, since they will add to the LTC1418 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 6MHz. Any noise that is present at the analog inputs will be summed over this entire bandwidth. Noisy input circuitry should be filtered prior to the analog inputs to minimize noise. For AC applications a simple 1-pole RC filter is usually sufficient. For example, a 1000pF capacitor
LTC1418
APPLICATIONS INFORMATION
from the input to ground and a 100 source resistor will limit the input bandwidth to 1.6MHz. Simple RC filters work well for AC applications, but they will limit the transient response. For full speed operation, a fast settling, low noise amplifier should be chosen. Internal Reference The LTC1418 has an on-chip, temperature compensated, curvature corrected, bandgap reference which is factory trimmed to 2.500V. It is internally connected to a reference amplifier and is available at Pin 3. A 8k resistor is in series with the output so that it can be easily overdriven in applications where an external reference is required, see Figure 2. The reference amplifier compensation pin (REFCOMP, Pin 4) must be connected to a capacitor to ground. The reference is stable with capacitors of 1F or greater. For the best noise performance, a 10F in parallel with a 0.1F ceramic is recommended. The VREF pin can be driven with a DAC or other means to provide input span adjustment. The reference should be kept in the range of 2.25V to 2.75V for specified linearity.
1 ANALOG INPUT 5V VIN VOUT LT1460 2 AIN- LTC1418 3 VREF AIN
+
OUTPUT CODE
OUTPUT CODE
4 10F 0.1F 5
REFCOMP
AGND
1418 F02
Figure 2. Using the LT1460 as an External Reference
UNIPOLAR / BIPOLAR OPERATION AND ADJUSTMENT Figure 3a shows the ideal input/output characteristics for the LTC1418. The code transitions occur midway between successive integer LSB values (i.e., 0.5LSB, 1.5LSB, 2.5LSB, ... FS - 1.5LSB). The output code is natural binary with 1LSB = FS/16384 = 4.096V/16384 = 250V. Figure 3b shows the input/output transfer characteristics for the bipolar mode in two's complement format.
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111...111 111...110 111...101 111...100
1LSB =
FS = 4.096V 16384 16384
000...011 000...010 000...001 000...000 0V
UNIPOLAR ZERO
1 LSB INPUT VOLTAGE (V)
FS - 1LSB
1418 F3a
Figure 3a. LTC1418 Unipolar Transfer Characteristics
011...111 011...110 BIPOLAR ZERO
000...001 000...000 111...111 111...110
100...001 100...000 -FS/2
FS = 4.096V 1LSB = FS/16384 -1 0V 1 LSB LSB INPUT VOLTAGE (V) FS/2 - 1LSB
1418 F3b
Figure 3b. LTC1418 Bipolar Transfer Characteristics
Unipolar Offset and Full-Scale Error Adjustment In applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. Offset error must be adjusted before full-scale error. Figures 4a and 4b show the extra components required for full-scale error adjustment. Zero offset is achieved by adjusting the offset applied to the AIN- input. For zero offset error apply 125V (i.e., 0.5LSB) at the input and adjust the offset at the AIN- input until the output code flickers between 0000 0000 0000 00 and 0000 0000 0000 01. For full-scale adjustment, an input voltage of 4.095625V (FS - 1.5LSBs) is applied to AIN+ and R2 is adjusted until the output code flickers between 1111 1111 1111 10 and 1111 1111 1111 11.
7
LTC1418
APPLICATIONS INFORMATION
R8 100 ANALOG INPUT R3 24k R4 100 R5 R2 47k 50k R6 24k 10F 0.1F 5 AGND VSS
1418 F04a
R7 48k 5V 1 AIN+ AIN- LTC1418 3 VREF VDD
R1 50k
2
4
REFCOMP
Figure 4a. Offset and Full-Scale Adjust Circuit if - 5V is Not Available
5V - 5V R1 50k R3 24k ANALOG INPUT R4 100 R5 R2 47k 50k R6 24k 10F 0.1F 5 AGND VSS
1418 F04b
1
AIN+ AIN-
VDD
2
LTC1418 3 VREF
4
REFCOMP
- 5V OR GND
Figure 4b. Offset and Full-Scale Adjust Circuit if - 5V is Available
Bipolar Offset and Full-Scale Error Adjustment Bipolar offset and full-scale errors are adjusted in a similar fashion to the unipolar case. Again, bipolar offset error must be adjusted before full-scale error. Bipolar offset error adjustment is achieved by adjusting the offset applied to the AIN- input. For zero offset error apply - 125V (i.e., - 0.5LSB) at AIN+ and adjust the offset at the AIN- input until the output code flickers between 0000 0000 0000 00 and 1111 1111 1111 11. For full-scale adjustment, an input voltage of 2.047625V (FS - 1.5LSBs) is applied to AIN+ and R2 is adjusted until the output code flickers between 0111 1111 1111 10 and 0111 1111 1111 11.
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BOARD LAYOUT AND GROUNDING Wire wrap boards are not recommended for high resolution or high speed A/D converters. To obtain the best performance from the LTC1418, a printed circuit board with ground plane is required. The ground plane under the ADC area should be as free of breaks and holes as possible, such that a low impedance path between all ADC grounds and all ADC decoupling capacitors is provided. It is critical to prevent digital noise from being coupled to the analog input, reference or analog power supply lines. Layout should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track. An analog ground plane separate from the logic system ground should be established under and around the ADC. Pin 5 (AGND) and Pin 14 (DGND) and all other analog grounds should be connected to this single analog ground point. The REFCOMP bypass capacitor and the VDD bypass capacitor should also be connected to this analog ground plane. No other digital grounds should be connected to this analog ground plane. Low impedance analog and digital power supply common returns are essential to low noise operation of the ADC and the foil width for these tracks should be as wide as possible. In applications where the ADC data outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get errors in the conversion results. These errors are due to feedthrough from the microprocessor to the successive approximation comparator. The problem can be eliminated by forcing the microprocessor into a wait state during conversion or by using three-state buffers to isolate the ADC data bus. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC1418 has differential inputs to minimize noise coupling. Common mode noise on the AIN+ and AIN- leads will be rejected by the input CMRR. The AIN- input can be used as a ground sense for the AIN+ input; the LTC1418 will hold and convert the difference voltage between AIN+ and AIN-. The leads to AIN+ (Pin 1) and AIN- (Pin 2) should be kept as short as possible. In applications where this is not
LTC1418
APPLICATIONS INFORMATION
possible, the AIN+ and AIN- traces should be run side by side to equalize coupling. SUPPLY BYPASSING High quality, low series resistance ceramic, 10F bypass capacitors should be used at the VDD and REFCOMP pins. Surface mount ceramic capacitors such as Murata GRM235Y5V106Z016 provide excellent bypassing in a small board space. Alternatively 10F tantalum capacitors in parallel with 0.1F ceramic capacitors can be used. Bypass capacitors must be located as close to the pins as possible. The traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. Power Shutdown The LTC1418 provides two power shutdown modes, nap and sleep, to save power during inactive periods. The nap mode reduces the power by 80% and leaves only the digital logic and reference powered up. The wake-up time from nap to active is 500ns (see Figure 5a). In sleep mode all bias currents are shut down and only leakage current remains-- about 2A. Wake-up time from sleep mode is much slower since the reference circuit must power up and settle to 0.005% for full 14-bit accuracy. Sleep mode wake-up time is dependent on the value of the capacitor connected to the REFCOMP (Pin 4). The wake-up time is 30ms with the recommended 10F capacitor. Shutdown is controlled by Pin 22 (SHDN); the ADC is in shutdown when it is low. The shutdown mode is selected with
SHDN t4 CONVST
1418 F05a
Figure 5a. SHDN to CONVST Wake-Up Timing
CS t3 SHDN
1418 F05b
Figure 5b. CS to SHDN Timing
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CS
25
CHIP SELECT 0V = NAP 5V = SLEEP SHUTDOWN INPUT 1M
SHDN LTC1418 D0 (EXT/INT)
22
20
D3 (SCLK)
17
1M
D4 (EXTCLKIN)
16
1M
1418 F05c
Figure 5c. Shutdown Circuit When Pins 16, 17 and 20 Are Not Driven
Pin 25 (CS); low selects nap (see Figure 5b), high selects sleep. Pins 16 (D4/EXTCLKIN), 17 (D3/SCLK) and 20 (D0/EXT/ INT) must be high (= VDD) or low (0V) during shutdown to avoid unwanted supply current from input buffers tied to these pins. If the pins are driven high or low during shutdown, unwanted current is avoided. If not, 1M pulldown resistors can be used as in Figure 5c. DIGITAL INTERFACE The LTC1418 can operate in serial or parallel mode. In parallel mode the ADC is designed to interface with microprocessors as a memory mapped device. The CS and RD control inputs are common to all peripheral memory interfacing. In serial mode only four digital interface lines are required, SCLK, CONVST, EXTCLKIN and DOUT. SCLK, the serial data shift clock can be an external input or supplied by the LTC1418 internal clock. Internal Clock The ADC has an internal clock. In parallel output mode the internal clock is always used as the conversion clock. In serial output mode either the internal clock or an external clock may be used as the conversion clock (see Figure 12). The internal clock is factory trimmed to achieve a typical conversion time of 3.4s and a maximum conversion time over the full operating temperature range of 4s. No external adjustments are required, and with the guaranteed maximum acquisition time of 1s, throughput performance of 200ksps is assured.
9
LTC1418
APPLICATIONS INFORMATION
Conversion Control Conversion start is controlled by the CS and CONVST inputs. A logic "0" applied to the CONVST pin will start a conversion after the ADC has been selected (i.e., CS is low, see Figure 6). Once initiated, it cannot be restarted until the conversion is complete. Converter status is indicated by the BUSY output. BUSY is low during a conversion.
CS t2 CONVST t1 RD
1418 F06
Figure 6. CS to CONVST Set-Up Timing
Data Output The data format is controlled by the SER/PAR input pin; logic low selects parallel output format. In parallel mode the 14-bit data output word D0 to D13 is updated at the end of each conversion on Pins 6 to 13 and Pins 15 to 20. A logic high applied to SER/PAR selects the serial formatted data output and Pins 16 to 20 assume their serial function, Pins 6 to 13 and 15 are in the Hi-Z state. In either parallel or serial data formats, outputs will be active only when CS and RD are low. Any other combination of CS and RD will three-state the output. In unipolar mode (VSS = 0V) the data will be in straight binary format (corresponding to the unipolar input range). In bipolar mode (VSS = - 5V), the
CS = RD = 0 tCONV (SAMPLE N) t5 CONVST t6 BUSY t7 DATA DATA (N - 1) DB13 TO DB0
Figure 7. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST =
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data will be in two's complement format (corresponding to the bipolar input range). Parallel Output Mode Parallel mode is selected with a logic 0 applied to the SER/ PAR pin. Figures 7 through 11 show different modes of parallel output operation. In modes 1a and 1b (Figures 7 and 8) CS and RD are both tied low. The falling edge of CONVST starts the conversion. The data outputs are always enabled and data can be latched with the BUSY rising edge. Mode 1a shows operation with a narrow logic low CONVST pulse. Mode 1b shows a narrow logic high CONVST pulse. In mode 2 (Figure 9) CS is tied low. The falling edge of CONVST signal again starts the conversion. Data outputs are in three-state until read by the MPU with the RD signal. Mode 2 can be used for operation with a shared databus. In slow memory and ROM modes (Figures 10 and 11), CS is tied low and CONVST and RD are tied together. The MPU starts the conversion and reads the output with the RD signal. Conversions are started by the MPU or DSP (no external sample clock). In slow memory mode the processor takes RD (= CONVST) low and starts the conversion. BUSY goes low forcing the processor into a wait state. The previous conversion result appears on the data outputs. When the conversion is complete, the new conversion results appear on the data outputs; BUSY goes high releasing the processor and the processor takes RD (= CONVST) back high and reads the new conversion data.
t8
DATA N DB13 TO DB0
DATA (N + 1) DB13 TO DB0
1418 F07
)
LTC1418
APPLICATIONS INFORMATION
CS = RD = 0 CONVST
t13
tCONV t5 t6 t8 t6
BUSY t7 DATA DATA (N - 1) DB13 TO DB0 DATA N DB13 TO DB0 DATA (N + 1) DB13 TO DB0
1418 F08
Figure 8. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST = )
CS = 0
(SAMPLE N) tCONV t5
CONVST t6 BUSY t9 RD t 10 DATA DATA N DB13 TO DB0
1418 F09
Figure 9. Mode 2. CONVST Starts a Conversion. Data is Read by RD
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t12 t8
t12
t11
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LTC1418
APPLICATIONS INFORMATION
CS = 0 (SAMPLE N) RD = CONVST t6 BUSY t10 DATA
tCONV
DATA (N - 1) DB13 TO DB0
Figure 10. Slow Memory Mode Timing
CS = 0 (SAMPLE N) RD = CONVST t6 BUSY t10 DATA
tCONV
DATA (N - 1) DB13 TO DB0
Figure 11. ROM Mode Timing
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t11
t7 DATA N DB13 TO DB0 DATA N DB13 TO DB0 DATA (N + 1) DB13 TO DB0
1418 F10
t8
DATA N DB13 TO DB0
1418 F11
LTC1418
APPLICATIONS INFORMATION
In ROM mode, the processor takes RD (= CONVST) low, starting a conversion and reading the previous conversion result. After the conversion is complete, the processor can read the new result and initiate another conversion. Serial Output Mode Serial output mode is selected when the SER/PAR input pin is high. In this mode, Pins 16 to 20, D0 (EXT/INT), D1 (DOUT), D2 (CLKOUT), D3 (SCLK) and D4 (EXTCLKIN) assume their serial functions as shown in Figure 12. (During this discussion these pins will be referred to by their serial function names: EXT/INT, DOUT, CLKOUT, SCLK and EXTCLKIN.) As in parallel mode, conversions are started by a falling CONVST edge with CS low. After a conversion is completed and the output shift register has been updated, BUSY will go high and valid data will be available on DOUT (Pin 19). This data can be clocked out either before the next conversion starts or it can be clocked out during the next conversion. To enable the serial data output buffer and shift clock, CS and RD must be low. Figure 12 shows a function block diagram of the LTC1418 in serial mode. There are two pieces to this circuitry: the conversion clock selection circuit (EXT/INT, EXTCLKIN and CLKOUT) and the serial port (SCLK, DOUT, CS and RD). Conversion Clock Selection (Serial Mode) In Figure 12, the conversion clock controls the internal ADC operation. The conversion clock can be either internal or external. By connecting EXT/INT low, the internal clock is selected. This clock generates 16 clock cycles which feed into the SAR for each conversion.
DATA IN 14
CLOCK INPUT SHIFT REGISTER
SAR
16 CONVERSION CLOCK CYCLES THREE STATE BUFFER 18
EOC
Figure 12. Functional Block Diagram for Serial Mode (SER/PAR = High)
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***
17 23
SCLK* RD CS
DATA OUT
25 THREE STATE BUFFER
19
DOUT*
CLKOUT*
***
16 20
EXTCLKIN* EXT/INT*
INTERNAL CLOCK 26 *PINS 16 TO 20 ARE LABELED WITH THEIR SERIAL FUNCTIONS BUSY
1418 F12
13
LTC1418
APPLICATIONS INFORMATION
To select an external conversion clock, tie EXT/INT high and apply an external conversion clock to EXTCLKIN (Pin 16). (When an external shift clock (SCLK) is used during a conversion, the SCLK should be used as the external conversion clock to avoid the noise generated by the asynchronous clocks. To maintain accuracy the external conversion clock frequency must be between 30kHz and 4.5MHz.) The SAR sends an end of conversion signal, EOC, that gates the external conversion clock so that only 16 clock cycles can go into the SAR, even if the external clock, EXTCLKIN, contains more than 16 cycles. When CS and RD are low, these 16 cycles of conversion clock (whether internally or externally generated) will appear on CLKOUT during each conversion and then CLKOUT will remain low until the next conversion. If desired, CLKOUT can be used as a master clock to drive the serial port. Because CLKOUT is running during the conversion, it is important to avoid excessive loading that can cause large supply transients and create noise. For the best performance, limit CLKOUT loading to 20pF. Serial Port The serial port in Figure 12 is made up of a 16-bit shift register and a three-state output buffer that are controlled by three inputs: SCLK, RD and CS. The serial port has one output, DOUT, that provides the serial output data. The SCLK is used to clock the shift register. Data may be clocked out with the internal conversion clock operating as a master by connecting CLKOUT (Pin 18) to SCLK (Pin 17) or with an external data clock applied to D3 (SCLK). The minimum number of SCLK cycles required to transfer a data word is 14. Normally, SCLK contains 16 clock cycles for a word length of 16 bits; 14 bits with MSB first, followed by two trailing zeros. A logic high on RD disables SCLK and three-states DOUT. In case of using a continuous SCLK, RD can be controlled to limit the number of shift clocks to the desired number (i.e., 16 cycles) and to three-state DOUT after the data transfer. A logic high on CS three-states the DOUT output buffer. It also inhibits conversion when it is tied high. In power shutdown mode (SHDN = low), a high CS selects sleep mode while a low CS selects nap mode. For normal serial port operation, CS can be grounded. DOUT outputs the serial data; 14 bits, MSB first, on the falling edge of each SCLK (see Figures 13 and 14). If 16 SCLKs are provided, the 14 data bits will be followed by two zeros. The MSB (D13) will be valid on the first rising and the first falling edge of the SCLK. D12 will be valid on the second rising and the second falling edge as will all the remaining bits. The data may be captured on either edge. The largest hold time margin is achieved if data is captured on the rising edge of SCLK. BUSY gives the end of conversion indication. When the LTC1418 is configured as a master serial device, BUSY can be used as a framing pulse and to three-state the serial port after transferring the serial output data by tying it to the RD pin. Figures 14 to 17 show several serial modes of operation, demonstrating the flexibility of the LTC1418 serial port.
SCLK
DOUT
1418 F13
Figure 13. SCLK to DOUT Delay
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LTC1418
APPLICATIONS INFORMATION
Serial Data Output During a Conversion Using Internal Conversion Clock for Conversion and Data Transfer. Figure 14 shows data from the previous conversion being clocked out during the conversion with the LTC1418 internal clock providing both the conversion clock and the SCLK. The internal clock has been optimized for the fastest conversion time, consequently this mode can provide the best overall speed performance. To select an internal conversion clock, tie EXT/INT (Pin 20) low. The internal clock appears on CLKOUT (Pin 18) which can be tied to SCLK (Pin 17) to supply the SCLK.
CONVST
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CONVST
(SAMPLE N) CS = EXT/INT = 0 CONVST t13 t6 BUSY (= RD) t10 1 CLKOUT (= SCLK) t7 DOUT Hi-Z D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FILL ZEROS D13 Hi-Z D13 D12 DATA N t11 SCLK
1418 F14b
t5
2
3
4
5
6
VIL t14 t15
DOUT
D13
Figure 14. Internal Conversion Clock Selected. Data Transferred During Conversion Using the ADC Clock Output as a Master Shift Clock (SCLK Driven from CLKOUT)
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BUSY RD SCLK
26 23 17
BUSY (= RD) P OR DSP (CONFIGURED AS SLAVE) OR SHIFT REGISTER
LTC1418 CLKOUT DOUT EXT/INT CS 25 18 19 20
CLKOUT ( = SCLK) DOUT
1418 F14a
(SAMPLE N + 1)
t8 HOLD SAMPLE HOLD
7
8
9
10
11
12
13
14
15
16
1
2
3
D11
DATA (N - 1) tCONV
D12 CAPTURE ON RISING CLOCK CAPTURE ON FALLING CLOCK
D11
VOH VOL
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LTC1418
APPLICATIONS INFORMATION
Using External Clock for Conversion and Data Transfer. In Figure 15, data from the previous conversion is output during the conversion with an external clock providing both the conversion clock and the shift clock. To select an external conversion clock, tie EXT/INT high and apply the clock to EXTCLKIN. The same clock is also applied to SCLK to provide a data shift clock. To maintain accuracy the conversion clock frequency must be between 30kHz and 4.5MHz. It is not recommended to clock data with an external clock during a conversion that is running on an internal clock because the asynchronous clocks may create noise.
CONVST
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CONVST
(SAMPLE N) CS = 0, EXT/INT = 5 CONVST t13 t6 BUSY (= RD) t10 1 EXTCLKIN (= SCLK) t7 DOUT Hi-Z D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FILL ZEROS D13 Hi-Z D13 D12 DATA N t11 SCLK
1418 F15b
t5
2
3
4
5
6
VIL t14 t15
DOUT
D13
Figure 15. External Conversion Clock Selected. Data Transferred During Conversion Using the External Clock (External Clock Drives Both EXTCLKIN and SCLK)
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BUSY RD
26 23
BUSY (= RD)
EXTCLKIN LTC1418 SCLK DOUT EXT/INT CS 25
16 EXTCLKIN ( = SCLK) P OR DSP 17 19 20 5V DOUT
1418 F15a
(SAMPLE N + 1)
t8 HOLD SAMPLE HOLD
7
8
9
10
11
12
13
14
15
16
1
2
3
D11
DATA (N - 1) tCONV
D12 CAPTURE ON RISING CLOCK CAPTURE ON FALLING CLOCK
D11
VOH VOL
LTC1418
APPLICATIONS INFORMATION
Serial Data Output After a Conversion Using Internal Conversion Clock and External Data Clock. In this mode, data is output after the end of each conversion but before the next conversion is started (Figure 16). The internal clock is used as the conversion clock and an external clock is used for the SCLK. This mode is useful in applications where the processor acts as a master serial device. This mode is SPI and MICROWIRE compatible. It
24 26 23 17
CONVST
CONVST
LTC1418 DOUT EXT/INT CS 25 19 20
CS = EXT/INT = 0 CONVST
t5
t6 BUSY HOLD t9
RD 1 SCLK t10 DOUT (SAMPLE N) tCONV DATA N
1418 F16b
Hi-Z
Figure 16. Internal Conversion Clock Selected. Data Transferred After Conversion Using an External SCLK. BUSY Indicates End of Conversion
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also allows operation when the SCLK frequency is very low (less than 30kHz). To select the internal conversion clock tie EXT/INT low. The external SCLK is applied to SCLK. RD can be used to gate the external SCLK, such that data will clock only after RD goes low and to three-state DOUT after data transfer. If more than 16 SCLKs are provided, more zeros will be filled in after the data word indefinitely.
BUSY RD SCLK
INT C0 SCK P OR DSP MISO
1418 F16a
t13 t8 SAMPLE
t12
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
t11 8 7 6 5 4 3 2 1 0 FILL ZEROS Hi-Z
D13 12 11 10 9
SCLK
VIL t14 t15
DOUT
D13
D12 CAPTURE ON RISING CLOCK CAPTURE ON FALLING CLOCK
D11
VOH VOL
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LTC1418
APPLICATIONS INFORMATION
Using External Conversion Clock and External Data Clock. In Figure 17, data is also output after each conversion is completed and before the next conversion is started. An external clock is used for the conversion clock and either another or the same external clock is used for the SCLK. This mode is identical to Figure 16 except that an external clock is used for the conversion. This mode allows the user to synchronize the A/D conversion to an external clock either to have precise control of the internal bit test timing or to provide a precise conversion time. As
CONVST 24 CONVST EXTCLKIN BUSY RD LTC1418 SCLK DOUT EXT/INT CS 25 17 19 20 5V
CS = 0, EXT/INT = 5 EXTCLKIN
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
t5 CONVST
t6 BUSY HOLD t9
RD 1 SCLK t10 DOUT (SAMPLE N) tCONV DATA N
1418 F17b
Hi-Z
Figure 17. External Conversion Clock Selected. Data Transferred After Conversion Using an External SCLK. BUSY Indicates End of Conversion
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in Figure 16, this mode works when the SCLK frequency is very low (less than 30kHz). However, the external conversion clock must be between 30kHz and 4.5MHz to maintain accuracy. If more than 16 SCLKs are provided, more zeros will be filled in after the data word indefinitely. To select the external conversion clock tie EXT/INT high. The external SCLK is applied to SCLK. RD can be used to gate the external SCLK such that data will clock only after RD goes low.
16 26 23
CLKOUT INT C0 P OR DSP SCK MISO
1418 F17a
1
2
3
4
t7
t13 t8 SAMPLE
t12
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
t11 8 7 6 5 4 3 2 1 0 FILL ZEROS Hi-Z
D13 12 11 10 9
SCLK
VIL t14 t15
DOUT
D13
D12 CAPTURE ON RISING CLOCK CAPTURE ON FALLING CLOCK
D11
VOH VOL
LTC1418
PACKAGE DESCRIPTION U
Dimensions in inches (millimeters) unless otherwise noted.
G Package 28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
0.397 - 0.407* (10.07 - 10.33) 28 27 26 25 24 23 22 21 20 19 18 17 16 15
0.301 - 0.311 (7.65 - 7.90)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 0.205 - 0.212** (5.20 - 5.38) 0.068 - 0.078 (1.73 - 1.99)
0 - 8
0.005 - 0.009 (0.13 - 0.22)
0.022 - 0.037 (0.55 - 0.95)
0.0256 (0.65) BSC
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0.010 - 0.015 (0.25 - 0.38)
0.002 - 0.008 (0.05 - 0.21)
G28 SSOP 0694
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LTC1418 RELATED PARTS
PART NUMBER ADCs LTC1274/LTC1277 LTC1415 LTC1416 LTC1419 LTC1605 DACs LTC1595 LTC1596 Reference LT1019-2.5 Precision Bandgap Reference 0.05% Max, 5ppm/C Max 16-Bit CMOS Multiplying DAC in SO-8 16-Bit CMOS Multiplying DAC 1LSB Max INL/DNL, 1nV * sec Glitch, DAC8043 Upgrade 1LSB Max INL/DNL, DAC8143/AD7543 Upgrade Low Power, 12-Bit, 100ksps ADCs Single 5V, 12-Bit, 1.25Msps ADC Low Power, 14-Bit, 400ksps ADC Low Power, 14-Bit, 800ksps ADC Single 5V, 16-Bit, 100ksps ADC 10mW Power Dissipation, Parallel/Byte Interface 55mW Power Dissipation, 72dB SINAD 75mW Power Dissipation, 80.5dB SINAD True 14-Bit Linearity, 81.5dB SINAD, 150mW Dissipation Low Power, 10V Inputs, Parallel/Byte Interface DESCRIPTION COMMENTS
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417 q (408) 432-1900 FAX: (408) 434-0507q TELEX: 499-3977 q www.linear-tech.com
1418i LT/TP 0198 4K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 1998

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